1. Field of the Invention
The present invention relates to collector-top type transistors, and more particularly to collector-top type transistors having the tunneling emitter structure.
2. Discussion of the Related Art
A variety of diversified high performance semiconductor devices are being realized in recent years as a result of advancement of the growth technology of multilayered thin film crystals of compound semiconductors. Among these, semiconductor devices generically termed the tunneling emitter transistors (TETs) equipped with an electron injection mechanism which utilizes the transmission plenomenon of the electron through a potential barrier by virtue of the quantum mechanical tunneling effect are being expected to be promising as the super-high speed semiconductor devices. The electron injection mechanism has a noteworthy significance in the semiconductor field having such aspects as it is applicable to heterojunction bipolar transistors (HBTs) and hot electron transistors (HETs) that are drawing attention as the next generation super-high speed devices, and further that it becomes possible to endow these devices with various kinds of functions by utilizing the resonance tunneling phenomenon obtainable by laminating a plurality of barrier layers.
Preparatory to a detailed description of the present invention, the conventional TET will be illustrated by using FIG. 1 and FIG. 2. As a common element which significantly limits the high speed performance of vertical semiconductor devices consisting basically of an emitter, a base, and a collector, one may mention the parasitic base-collector capacitance. In order to suppress the parasitic capacitance to a possible minimum, it has been known that the collector-top type device in which the collector is positioned above the emitter is more advantageous than the emitter-top type device with reversed arrangement. The emitter-top type device shown in FIG. 1 has a bipolar transistor structure in which the semiconductor layers of n.sup.+ -GaAs as a collector contact layer 7, n.sup.- -GaAs as a collector layer 6, p.sup.+ -GaAs as a base layer 5, i-Al.sub.0.5 Ga.sub.0.5 As as a tunnel barrier layer 4, n-GaAs as an emitter layer 3, and n.sup.+ -GaAs as an emitter contact layer 2 are laminated sequentially on a semi-insulating semiconductor substrate 1. Such an emitter-top type TET has been disclosed in Japanese Patent Application Laid-Open No. 62-130561.
In this case, the base-collector capacitance that is generated in the plane of the base-collector junction is not limited to the intrinsic transistor region 18 but extended even to the extrinsic transistor region 19, so that the large value of the base-collector capacitance restricts the high-speed performance of the TET to a great extent.
On the other hand, in the case of the collector-top type device shown in FIG. 2, the order of lamination of the semiconductor layers is the opposite to that of the emitter-top type device. The base-collector capacitance is generated solely from the intrinsic transistor region 18 so that a substantial improvement of the high-speed performance might be expected.
However, while the device structure of the collector-top type has an advantage of suppressing the parasitic base-collector capacitance to a possible minimum, carrier (electron in this example) injection from the emitter to the base takes place as may be seen from FIG. 2 not only in the intrinsic transistor region 18 (area designated by an electron 17a in the figure) but also in the extrinsic transistor region 19 (area designated by electrons 17b in the figure). Electrons injected through the latter region not only do not contribute to the transistor operation but reduce the current gain to a large extent, which has been a drawback of the collector-top type device structure.